Recent changes to Project Bochs x86 PC emulator

#360 New instrumentation call for DMA transfers

2026-11-10T20:19:25.872000Z

status: open --> closed
Group: --> applied_to_SVN

#360 New instrumentation call for DMA transfers

2026-11-10T20:19:05.625000Z

Implemented in git

#236 [PATCH] rewrite eth_fbsd.cc (using netgraph)

2026-11-08T20:35:44.661000Z

Description has changed:

Diff:

--- old
+++ new
@@ -1,4 +1,3 @@
-
   By using netgraph, some limitations from bpf method 
 are removed. Bochs
 ne2k works as it were a real adapter attached on the

status: open --> closed
Group: --> rejected

#236 [PATCH] rewrite eth_fbsd.cc (using netgraph)

2026-11-08T20:35:30.912000Z

obsolete, if you have updated one - please submit in github

#478 Display Host/Guest mode on GUI debugger

2026-11-04T20:50:13.154000Z

status: open --> closed
assigned_to: Stanislav Shwartsman
Group: --> applied_to_SVN

#478 Display Host/Guest mode on GUI debugger

2026-11-04T20:50:02.537000Z

Implemented different way now

#419 Save and restore window positions

2026-10-31T15:08:29.750000Z

status: open --> wont-fix
Group: --> nice_to_have

#1181 PCI interrupts go to multiple IOAPIC entries w/ bad trigger

2026-10-28T16:27:05.256000Z

What the report says, against current code

PCI interrupts do still reach two I/O APIC inputs:
pci_set_irq() drives input 16 + pirq (pci2isa.cc:224).
The routed ISA IRQ then goes through DEV_pic_set_irq_level(). raise_irq() and lower_irq() forward it to I/O APIC input X (pic.cc:498, pic.cc:474).
The recent fixes didn’t change this dual routing. They are 79b10b2b9 (Remote IRR, moving asserted PIRQ lines when the routing changes), 862acecfa (a level-triggered entry whose line is already high is pending) and 52662b8fc. They do make level-triggered delivery on input X more correct.

Why it’s not really a bug

The I/O APIC never picks a trigger mode itself; the guest programs it. Bochs reports input 16–19 interrupts in neither its MP table nor its ACPI tables:
ACPI: _PRT sends every PCI pin through the LNKA–LNKD link devices to ISA IRQs (Level, ActiveLow). There’s no _PIC method and no input 16+ routing, so an ACPI guest in APIC mode always uses input X.
MP table: it has only 15 ISA entries with flags 0 (bus default, which means edge / active high for ISA) and no PCI bus interrupt entries (rombios32.c:1377).
So guests always use input X. Input X forwarding can’t be removed without breaking every APIC-mode guest; QEMU’s PIIX model works the same way. Inputs 16–19 stay masked from reset, so a second interrupt can only happen if the guest unmasks them itself.

What’s left of the complaint
The reporter’s “bad trigger” comes from the MP table. A guest that uses only the MP table is told that PCI IRQs 9 and 11 are edge-triggered ISA interrupts, while the ELCR marks them level-triggered (rombios32.c:865). With a shared line in edge mode, an interrupt can be lost if a second device asserts while the line is already high.

#1336 Sending EOI to Local APIC acts that all interrupts is complete

2026-10-26T21:16:26.276000Z

status: unread --> closed
Group: can't_reproduce --> fixed_in_SVN

#1336 Sending EOI to Local APIC acts that all interrupts is complete

2026-10-26T21:16:12.653000Z

Fixed by 4e4a0f309 and 79b10b2b9 / 1cd5b8d5e